AMD Ryzen Strix Point spotted with Zen 5, increasing L1 data cache

Company AMD is preparing a new generation of its Ryzen processors, which will be built on the architecture Zen 5. It will be both desktop and mobile models, while the mobile ones should be represented by the Strix Point series. Next to the Strix Point Halo, which is supposed to have up to 16 Zen 5 cores and a very powerful iGPU with up to 40 CU, it will mainly be normal Strix Point. These processors should have a maximum of 12 cores, and it will be a hybrid architecture with Zen 5 and Zen 5c cores. Integrated graphics with RDNA 3.5 architecture should have an increased number of CUs from 12 to 16 (against Hawk Point) and an NPU built on XDNA 2 with a performance of around 45-50 TOPS. Now a record of one of these processors has appeared. It was an engineering sample, i.e. a processor that is not yet final and usually runs at lower clocks than later commercially available versions.

This processor showed up in the Geekbench 5.4.6 benchmark database and was set to 28W TDP. The base frequency was supposed to be 2.0 GHz, but the processor even ran at an even lower clock rate of only 1.4 GHz. Nevertheless, he showed quite an interesting performance. The ST single-core result was 1217 points, the multi-core MT 8016. These are very low values ​​in themselves (the 8-core Ryzen 9 8945 HS has 12300 points in MT, but it also achieves much higher clocks, even 5.2 GHz on one core), however, considering the frequencies of the engineering sample, these are pretty decent numbers. But the results of other versions that will already run with normal frequencies will be interesting.

With the new Strix Point processors, we will also see that the capacity of the L1 data cache increases from 32 KB to 48 KB, while the instruction cache remains at 32 KB. L2 cache will continue to be 1 MB per core, L3 cache will be 24 MB overall (16 MB for Zen 5 and 8 MB for Zen 5c cores).