DDR5 memories will speed up to almost 9 GHz and get protection against the malicious Rowhammer attack

A few days ago we lamented here how LPDDR5X memories for laptops and mobiles lost in performance (or more precisely in effective frequency and throughput) to the common DDR5 memory we have in desktop PCs. The new improved version of DDR5 standard memories, now released by JEDEC, is supposed to improve it a bit. It will significantly raise the current frequencies and reach almost twice where these memories started in 2021.

DDR5-8800

JEDEC is the standardization organization for various memory technologies, including DDR5. Now this consortium has released an update to the DDR5 standard that expands the originally planned frequency range from the original 3200-6800 MHz (effectively). The new update adds gears up to DDR5-8800, an effective 8.8GHz if you will. It is probably more accurate to talk about a transfer rate of 8.8 Gb/s per one bit of width, but this is again confused with the total memory throughput.

The standard defines not only this highest speed, but also intermediate steps stepped after 400 MHz from the maximum 8800 MHz through 8400, 8000 MHz and so on down to the lowest standardized (but probably not used much in practice) DDR5-3200 speed. Standard timings are then defined for these timings. For DDR5–8800 it should be CL62–62–62.

When using two modules (i.e. with a total width of 128 bits, which we traditionally refer to as a two-channel connection (but with DDR5 it is internally solved as a four-channel)), the theoretical bandwidth of DDR5-8800 memories will already be 140.8 GB/s, which would not be without attractiveness for the integrated graphics of more powerful APUs, but the question is whether more expensive fast memories will be used with them.

However, higher throughput should help processors with high core counts, such as the 16-core Ryzen 9 or Intel’s 24-core big.LITTLE processors. For multi-threaded applications, with such powerful CPUs in mainstream platforms, the bandwidth of memories with a width of only 128 bits may be the limit. DDR5-8800 is a nearly 47% throughput improvement over DDR5-6000.

But before DDR5-8800 is officially supported by some processors, it may take quite some time. At Intel, Raptor Lake officially supports the DDR5-5600 frequency, and the next-generation Arrow Lake is said to officially support DDR5-6400. AMD’s Ryzen 7000 and 8000 now support DDR5-5200. The new Ryzen 9000s with the Zen 5 architecture probably won’t push it much higher, because they use the same IO chiplet as Zen 4. In the future, standard support for such memories could only be available in Zen 6.

However, these frequencies and timings only apply to modules according to the JEDEC standard – these are the frequencies used by OEM PCs and notebooks, for example. In gaming computers, it has long been the norm not to use memory with standard JEDEC frequencies, but instead memory is overclocked using the Intel XMP or AMD EXPO profiles. They usually set the frequencies higher and, on the contrary, shorten the timing and thereby shorten the access latency. On the other hand, they usually pay for it by increasing the voltage beyond the standard, and thus also increasing consumption.

Standard DDR5–8800 CL 62–62–62 memories should therefore also bring with them even faster overclocked modules based on XMP and EXPO. These should have clocks over 9 GHz and possibly even over 10 GHz (effectively).

Protection against Rowhammer

However, this new version of the specifications for DDR5 has one more important novelty even for those who are not chasing the highest possible frequencies and bandwidths. The specification introduces a function Per-Row Activation Counting (WORK). It is a counter that tracks the number of activations for each wordline in the chip. The memory can thus detect that there is an excessive number of these accesses on a wordline.

This is intended to help protect against RowHammer attacks, which are capable of flipping bits in adjacent wordlines by constantly accessing certain memory addresses, leading to data corruption in those parts of memory and either crashing programs or cleverly manipulating a security breach. PRAC should detect that a RowHammer attack is occurring on a system, and the processor or operating system can then force more frequent refreshes of the affected addresses to prevent bit flipping.

Unfortunately, it is not a complete solution to this very annoying hardware vulnerability, but at least somehow this feature could help against Rowhammer. So these new memories should be quite useful in servers where the risk of exploiting this DRAM memory weakness is greatest.

Sources: JEDEC, AnandTech