Zen 5 up to 40% faster than Zen 4?


It’s exactly 6 years to the month since Mike T. Clark, the architect of the first A woman (and perhaps Zen 4), during the interview he uttered the sentence “As an architect, I am already working on Zen 5…” which started a wave of reflections and speculations, which basically has not ended to this day.

generation code name process architect period
Zen Zen 14 nm Mike T. Clark Q1 2017
Zen+ 12 nm Q2 2018
Zen 2 Valhalla 7 nm David Suggs Q3 2019
Zen 3 Cerebrus 7 nm Mark Evers Q4 2020
Zen 3+ 6 nm Q1 2022
Zen 4 Persephone 5nm, 4nm Mike T. Clark? Q3 2022
Zen 5 Nirvana 4nm, 3nm David Suggs Q3 2024
Zen 6 Morpheus 3nm, 2nm ? Q1 2026?

Much more is known today than six years ago. We know that Zen 5 is an architecture focused on IPC (rather than clock rates). We do know that it will offer more (6) ALUs, improved support for instructions and data formats (eg FP16, faster AVX-512) and will be built on TSMC’s 4nm process, which is only a slight improvement over the 5nm manufacturing used by the current Zen 4.

April 2024 is not only the six-year anniversary since the first mention of this architecture, but also a year since AMD ran the first sample in the labs Zen 5.

Practically since last year, there have been debates on the topic of the intergenerational increase in IPC, fueled by apparent contradictions between the leaked roadmap talking about at least 10-15%, and information from AMD partners, to whom AMD should have mentioned (at least?) 15-20% sometime last year in addition and finally sketchy rumors that talk about 30 or even 40%. Where is the truth?

AMD roadmap mentioning IPC increase of at least 10-15% (via MLID)

The mention of 10-15% in the roadmap needs to be understood in the context of the given message. First of all, it is necessary to notice that the wording for expected products is different from the wording for released (“achieved”) and also the “+” symbol, which defines that the values ​​of 10-15% are not the range in which the IPC will move, but the minimum that AMD wants to exceed.

The mention of the 15-20% range that AMD told partners last year will be closer to reality, but its aim was probably nothing more than to convey that the increase in IPC will be higher than Zen 4, but at the same time not to create excessive expectations and vain hopes in case everything does not go according to plan (unfulfilled promises usually cause more disappointment than keeping even a slightly below-average intergenerational increase). Let us remind you that AMD chose a similarly cautious approach when promoting previous generations, for example with the original one A woman it announced “up to a 40% increase in IPC” and eventually presented an average increase of 52%. AT Zen 2 mention was made of more than 10% and the final value was 15%, and it can also be recalled Zen 4where mention was made of an 8% increase in Cinebench, which ultimately turned out to be the worst case scenario for this architecture, while the average was around 13%, around 14% after firmware tuning.

Long-time leaker Kepler_L2 reported on the Anandtech discussion forum that in an (unspecified suite test) SPEC achieves Zen 5 with the same number of cores as it has Zen 4 40% higher performance. This is far from the first report to suggest an increase in IPC over 20%, but the number is increasing and this source is relatively reliable. However, it remains important not to confuse performance (which Kepler is talking about) with IPC, and to keep in mind that we don’t know which test from the SPEC suite the performance increase was measured on. In practically every generation of architectures (Zen 3, Alder Lake, Zen 4…) found an application (sometimes even from the SPEC suite) where there was a high increase in IPC (~30-60%), while the average increase in IPC was more like half. Similar sketchy data should therefore be understood in the given context and not generalized.

Let’s go back to the difference between performance and IPC. Usually, IPC is understood as the power achieved per unit of clock frequency. In other words performance = IPC x tact. In practice, the situation is more complicated, as more and more variables affect it. With the last generations, especially the increase in the number of cores, when the performance in the load of all cores can be significantly more limited by the arrangement of the cores, the structure of shared caches and, on the other hand, the specific ratio between the clocks actually achieved with a single-core boost and with the boost of all cores. Even if we compare, let’s give it the performance of a 16-core Zen 4 with a maximum clock of 5.5 GHz with 16 cores Zen 5 with a maximum clock of 5.5 GHz, the intergenerational difference in single-core load can achieve significantly different results than the intergenerational difference in total load. In the second case, the unknown will play a role in the form of a real clock (multi-core boost) and, moreover, architectural changes that may not manifest themselves when a single core is under load (e.g. the speculated redesigned L3 cache structure).

For example, if in a single-core load the average increase in IPC / performance (assume ± the same maximum clocks for both generations) would be around 25%, in a multi-core load the performance increase might be ~30%, and in a particular application that the architecture will fit above average, then it can even a ~40% increase can easily occur. However, you definitely cannot equate one (an unspecified figure) with the average IPC of an architecture in a truly single-core (more precisely, single-threaded) load.

The article is in Czech

Tags: Zen faster Zen


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